Flat panel displays have become increasingly important in appliances requiring lightweight portable screens. Currently, such screens use electroluminescent or liquid crystal technology. A promising technology is the use of a matrix-addressable array of cold cathode emission devices to excite phosphor on a screen.
In field emission display (FED) technology, glass substrates with evaporated molybdenum tips have been fabricated according to the "Spindt" process which was disclosed in U.S. Pat. Nos. 3,665,241, and 3,755,704, and 3,812,559 and 5,064,396. This process has the drawback that the integrated circuit drivers are not possible on the same substrate as the tips.
A process for constructing emitter tips of silicon, typically &lt;100&gt; orientation, is described in U.S. Pat. application Serial No. 837,833, entitled "Method of Creating Sharp Asperities and other Features on the Surface of a Semiconductor Substrate," having the same assignee as the present application. While this approach has merit in that it allows the formation of integrated circuits which lowers the cost of the drivers, as well as the complexity of the drivers, it also has a drawback which is the relatively high cost of the substrates currently available. Through the use of a relatively thick substrate of macro-grain polycrystalline silicon according to the present invention, the best of the low-cost and integrated drivers can be realized.
Macro-grain polysilicon is relatively easy to make. Molten silicon is simply allowed to cool. The size of the grains is dependent on the rate of cooling. The faster the silicon cools, the smaller the grains. The manufacturing process is less sensitive and less time consuming than making monocrystalline wafers, and as a result, the macro-grain wafers cost less. In fact, macro-grain polysilicon is even cheaper than using a glass substrate. This is because high temperature glass is the preferred glass for the fabrication of flat panel displays, and such glass is more costly than macro-grain polysilicon.
A great deal of research has been conducted in the area of large grain amorphous silicon substrates which are comparatively thin (i.e. less than 1 micron) for use in liquid crystal displays (LCD's). The amorphous silicon does not have a definite arrangement of the silicon atoms. A representative grain size would be in the range of 50 nm, although grain sizes used in such research do vary significantly.
In contrast, the present invention relates to macro-grain polycrystalline substrates which are relatively thick (i.e. greater than 300 microns). In such a case, the atoms are arranged in unit cells, but the unit cells are not in a regular arrangement with each other, and the cells have very large grain boundaries. Macro-grain being defined as a substrate in which less than 1% of the crystal grains are smaller than 0.5 mm.
The grain boundaries are essentially defects in the substrate, and the present invention provides a means for overcoming these substrate defects, and effectively using the substrate in a flat panel display unit. The grain boundaries represent a change in the orientation of the crystalline structure of the substrate. First quality silicon wafers have a single crystal (or monocrystalline) orientation, and are the desired substrate for integrated circuit fabrication.
One of the problems which results from the presence of grain boundaries is the unpredictability in etching steps. When the etching material hits a grain boundary, the material is hindered, and the result of the etch step is a often a defective device. On a wafer containing many integrated circuit devices, the loss of a single chip may not be a significant commercial loss. However, in the fabrication of flat panel display devices, a single defect can result in the loss of the whole wafer, since the wafer as a whole is commonly employed in the display unit. A device defect appears as a black spot or line through the screen, and thus makes the entire unit unmarketable.
One advantage of macro-grain polysilicon substrates is their availability in relatively large sizes at comparatively low costs. A further advantage is that macro-grain substrates are adaptable to high temperature processing. A still further advantage of macro-grain polysilicon substrates is that such substrates have a thermal co-efficient of expansion which matches the co-efficient of expansion of the active silicon devices which are fabricated thereon.
Another further advantage of the present invention is that the use of redundant circuitry on a macro-grain substrate will tend to improve the yield because such redundant circuitry compensates for the possibility that a device is inadvertently placed at a major grain boundary.